01May 2026
FPGA Signal Processing Pipeline
Designed a 25-tap complex FIR and CORDIC accelerator on a Zynq FPGA to calculate magnitude and phase from complex input signals.
57 → 5FIR latency, cycles
Loop unrolling, array partitioning, and HLS pipelining raised estimated Fmax from 141.7 to 165.6 MHz. Fixed-width and fixed-point arithmetic reduced DSP use by 93%, FFs by 86%, and LUTs by 83% versus the standard integer/double implementation.
Vivado / VitisHLSap_fixed
02May 2026
8-Bit Carry Skip Adder
Architected a two-stage pipelined CMOS adder in Cadence Virtuoso, verified with transient simulation and worst-case timing analysis.
504.7 pscritical-stage delay
Debugged bus timing glitches and optimized pipeline register behavior to improve signal integrity and timing consistency.
Cadence VirtuosoCMOSTiming analysis
03December 2025
Permafrost Freeze & Thaw
Led a five-person capstone team to build a Peltier-based soil freeze–thaw platform supporting AFOSR-funded permafrost research in Alaska.
Integrated Keysight VNA measurements to analyze S11 frequency response during thermal cycling, enabling repeatable laboratory thermal and RF characterization experiments.
Team leadershipRF measurementThermal systems
04December 2025
Smart Auto Camera
Built an autonomous object-tracking camera using a Raspberry Pi 5 and ESP32-controlled servos.
Combined Python, OpenCV motion detection, and YOLO object recognition with a custom soldered control circuit and 3D-printed camera and servo mounts.
Python / OpenCVYOLORaspberry Pi / ESP32